1. FIELD OF THE INVENTION
The present invention relates to a PCM record reproducer for reproducing a magnetic tape in which pulse code modulation signals (codified sound signal) are recorded. More particularly, it relates to an edition detecting process wherein data are edited in a magnetic tape.
2. DESCRIPTION OF THE PRIOR ART
FIG. 1 shows a conventional PCM record reproducer. In FIG. 1, the reference numeral (1) designate an analogue signal input terminal; (2) designates an analogue-digital converter; (61) designates a coder circuit for allotting PCM signal data given by the analogue-digital converter (2) into multi-tracks and adding each code for detecting error in each number of PCM signals in each track; (5) designates a modulator circuit for recording PCM signals in the magnetic tape; (6) designates a recording head; (7) designate the magnetic tape; (8) designates a reproducing head; (9) designates a demodulator circuit for demodulating the output reproduced by the reproducing head (8) into PCM signals; (10) designates a circuit for detecting error of the reproduced PCM signal; (12) designates a splice detector circuit for detecting the edited point (hereinafter referring to as splice point); (62) designates a parallel-serial converter circuit for arranging PCM signals in the multi-tracks into serial PCM signals having the same form as at the recording; (26) designates a signal processor circuit for connecting the PCM signals near the splice point without any level-jumping by the signal of the splice detector circuit (12); (27) designates a memory circuit and the timing for read-out and write-in of the memory is controlled by a memory controller circuit (28); (29), (30) respectively designate clock generator circuits for controlling the PCM record reproducer; (31) designates quartz; (32) designates a selector circuit for switching clocks from the clock generator circuits (29), (30) by the signal of the memory controller circuit (28); (33) designates a servo controller circuit for controlling the running of the magnetic tape depending upon the clock selected by the selector circuit (32); (34) designates an output terminal to the servo system; (15) designates a digital-analogue converter circuit; and (16) designates an output terminal of the analogue signal.
The operation will be illustrated.
In order to simplify the discussion, in FIG. 1 the number of the tracks is 4; and the number of frames of the PCM signals is 4.
The analogue signals input from the input terminal (1) are converted in PCM signals by the analogue-digital converter (2).
The PCM signals in the part (i) in FIG. 1 are converted into the data shown in FIG. 9(a) wherein the references (b.sub.1), (b.sub.2) . . . show PCM signals arranged in time. The PCM signals are allotted to the tracks by the track allotting and error detecting coder (61); and the synchronous mark (a) is also added. The format of the output (j) in FIG. 3 is shown in FIG. 9(b) wherein the references (d.sub.1), (d.sub.2), (d.sub.3), (d.sub.4) designate error detection codes. The output of the coder circuit (61) is modulated for recording into the magnetic tape (7) by the modulator circuit (5) and recorded into the magnetic tape (7) by the recording head (6).
The reproduction will be illustrated.
The signals are read-out from the magnetic tape (7) by the reproducing head (8) and converted into the PCM signals by the demodulator circuit (9) and any error is detected by the error detector circuit (10) and the signals are converted by the parallel-serial converter circuit (62).
The operation for normal reproduction for a non-splice point will be illustrated.
Two PCM signals as the output of the parallel-serial converter circuit (62) are treated by the signal processor circuit (26) to collect data and delayed by the memory circuit (27). The PCM signals are converted into analogue signals by the digital-analogue converter (15) and fed out from the output terminal (16).
The operation for reproduction for the magnetic tape having a splice point will be illustrated.
When the splice point is detected by the splice detector circuit (12), the memory controller circuit (28) stops the write-in clock whereby the operation for write-in of the error data at the splice point in the memory circuit (27) is stopped. On the other hand, when the read-out from the memory circuit (27) for the error at the splice point is finished, the memory controller circuit (28) actuates the write-in clock of the memory circuit (27) thereby starting the write-in of the PCM signal for processing to connect smoothly the data in the front and back part of the splice point, into the memory circuit (27). Therefore, the error at the splice point is not written-in the memory circuit.
The memory quantity for the PCM signals in the memory circuit is reduced by the signal processing at the splice point and accordingly, it is necessary to fill PCM signals into the memory circuit.
The additional feed of the PCM signals for filling into the memory circuit (27) will be illustrated.
The memory quantity in the memory circuit (27) is always detected by the memory controller circuit (28). When the memory quantity in the memory circuit is reduced from a predetermined value by the processing at the splice point, the clock of the second clock generator circuit (30) is selected.
On the other hand, the clock of the first clock generator circuit (29) is used as the read-out clock of the memory circuit and the clock of the digital-analogue converter. The clock of the second clock generator (30) is slightly faster than the clock of the first clock generator circuit, whereby the tape running speed and the rate signal write-in in the memory circuit increases relative to the read-out rate of from the memory circuit to fill the memory quantity. When the memory quantity increases over a predetermined value, the memory control circuit (28) feeds the control signal to the selector circuit (32) so as to select the clock of the first clock generator circuit.
The operation of the signal processor circuit (26) will be illustrated.
In FIG. 2, the reference number (51) designates an input terminal for PCM signals; (52), (54) respectively designate first and second memories for potentially memorizing PCM signals; (58) designates an address circuit for controlling the write-in of the memories (52), (54); (53), (55) respectively designate multipliers; (59) designates a significance generator for generating coefficients for the multipliers (53), (55); (56) designates an adder; (57) designates an output and (60) designates an input terminal for the splice detecting signal.
In the non-splice detection, the signal processor circuit (26) usually operates such that the input signal passed through the first memory (52) is multiplied by a factor of one (.times.1) by the first multiplier circuit (53) and the input signal of the second memory (54) is multiplied by a factor of zero (.times.0) by the second multiplier (55) and the sum is given by the adder (54). The same signals as that of the input are thereby fed out from the output terminal (57).
The operation will be illustrated.
The address circuit (58) is operated by inputting the splice detecting signal from the terminal (60) to stop the write-in and read-out of the first memory (52). On the other hand, it is operated to continue the write-in of the second memory (54). When the splice signal is finished, the address circuit (58) is operated so as to start again the write-in and read-out of the first memory (52). At this moment, the memorized data in the second memory (52) are the PCM signals in the post-splice point. The output PCM signals of the first memory (52) fade-out by sequentially reducing the multiplying factor of the first multiplier (53) from .times.1 to .times.0. On the other hand, the output PCM signals of the second memory (54) fade-in by sequentially increasing from .times.0 to .times.1 the multiplying factor of the second multiplier (55). The control is carried out by the significance generator circuit (22).
The outputs of the multiplier circuits are added by the adder circuit (56) and the sum output from the output terminal (57).
The conventional PCM record reproducer has the above-mentioned structure and accordingly, it has been disadvantageously necessary to vary the tape running speed and to need two kinds of the clock generator circuits. It has been considered to record PCM signals on a magnetic tape by delaying one of the signals in multiple state during editing to prevent an error at a splice point so as to connect the data in the pre-splice point and the post-splice point. This operation, however, disadvantageously requires high record density in the magnetic tape.